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Your search returned 280 patents.
( 712/237 in Current US Classification ) |
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| 1 2 3 |
| Patent ID | Title | Date Filed |
| 6725335 | Method and system for fast unlinking of a linked branch in a caching dynamic translator
| January 5, 2001 |
| 6721855 | Using an L2 directory to facilitate speculative loads in a multiprocessor system
| June 26, 2002 |
| 6718839 | Method and apparatus for facilitating speculative loads in a multiprocessor system
| June 26, 2002 |
| 6715063 | Call gate expansion for 64 bit addressing
| January 14, 2000 |
| 6704860 | Data processing system and method for fetching instruction blocks in response to a detected block sequence
| July 26, 2000 |
| 6704859 | Compressed instruction format for use in a VLIW processor
| August 4, 1998 |
| 6675374 | Insertion of prefetch instructions into computer program code
| October 12, 1999 |
| 6675288 | Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
| May 9, 2002 |
| 6658534 | Mechanism to reduce instruction cache miss penalties and methods therefor
| March 31, 1998 |
| 6647491 | Hardware/software system for profiling instructions and selecting a trace using branch history information for branch predictions
| October 1, 2001 |
| 6647490 | Training line predictor for branch targets
| October 14, 1999 |
| 6647487 | Apparatus and method for shift register rate control of microprocessor instruction prefetches
| February 18, 2000 |
| 6636945 | Hardware prefetch system based on transfer request address of cache miss load requests
| July 19, 2001 |
| 6633974 | Apparatus and method for controlling link stack corruption during speculative instruction branching using multiple stacks
| November 4, 1999 |
| 6629235 | Condition code register architecture for supporting multiple execution units
| May 5, 2000 |
| 6622240 | Method and apparatus for pre-branch instruction
| February 1, 2000 |
| 6622236 | Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions
| February 17, 2000 |
| 6615339 | VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively
| January 18, 2000 |
| 6611910 | Method for processing branch operations
| October 12, 1998 |
| 6606701 | Micro-processor
| November 24, 1999 |
| 6598154 | Precoding branch instructions to reduce branch-penalty in pipelined processors
| December 29, 1998 |
| 6594730 | Prefetch system for memory controller
| August 3, 1999 |
| 6591360 | Local stall/hazard detect in superscalar, pipelined microprocessor
| January 18, 2000 |
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