| 1 2 3 4 5 |
| Patent ID | Title | Date Filed |
| 7082518 | Interruptible digital signal processor having two instruction sets
| October 16, 2001 |
| 7065635 | Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor
| December 17, 2003 |
| 7058741 | System for suspending processing by a first electronic device on a data line to allow a second electronic device to use the data line, with subsequent resumption of the processing of the first electronic device
| July 29, 2002 |
| 7055151 | Systems and methods for multi-tasking, resource sharing and execution of computer instructions
| December 9, 1999 |
| 7051181 | Caching for context switching applications
| January 14, 2005 |
| 7036002 | System and method for using multiple working memories to improve microprocessor security
| June 25, 1998 |
| 7035999 | Register window fill technique for retirement window having entry size less than amount of fill instructions
| June 7, 2002 |
| 7032104 | Configurable hardware register stack for CPU architectures
| December 15, 2000 |
| 7024541 | Register window spill technique for retirement window having entry size less than amount of spill instructions
| June 7, 2002 |
| 7020768 | Apparatus and method for facilitating debugging of sequences of processing instructions using context identifier comparison
| February 26, 2001 |
| 7013377 | Method and apparatus for alleviating register window size constraints
| September 3, 2003 |
| 7010674 | Efficient handling of a large register file for context switching and function calls and returns
| March 19, 2001 |
| 6996735 | Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an unprotected pipeline
| November 22, 2002 |
| 6990658 | Method for translating instructions in a speculative microprocessor featuring committing state
| October 13, 1999 |
| 6988186 | Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to acc | June 28, 2001 |
| 6986142 | Microphone/speaker system with context switching in processor
| September 14, 2000 |
| 6986141 | Context controller having instruction-based time slice task switching capability and processor employing the same
| December 17, 1998 |
| 6986028 | Repeat block with zero cycle overhead nesting
| July 17, 2002 |
| 6983467 | Application programming interface enabling application programs to group code and data to control allocation of physical memory in a virtual memory system
| September 2, 2004 |
| 6983359 | Processor and method for pre-fetching out-of-order instructions
| August 13, 2003 |
| 6981261 | Method and apparatus for thread switching within a multithreaded processor
| September 20, 2002 |
| 6981083 | Processor virtualization mechanism via an enhanced restoration of hard architected states
| December 5, 2002 |
| 6976155 | Method and apparatus for communicating between processing entities in a multi-processor
| June 12, 2001 |
| 6973552 | System and method to handle page validation with out-of-order fetch
| May 12, 2003 |
| 6971104 | Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction
| September 20, 2002 |
| 6971103 | Inter-thread communications using shared interrupt register
| April 1, 2003 |
| 6968476 | Checkpointing a superscalar, out-of-order processor for error recovery
| June 26, 2002 |
| 6968469 | System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
| June 16, 2000 |
| 6965986 | Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate
| September 19, 2002 |
| 6957326 | Methods and apparatuses for executing threads
| June 27, 2002 |
| 6954846 | MICROPROCESSOR AND METHOD FOR GIVING EACH THREAD EXCLUSIVE ACCESS TO ONE REGISTER FILE IN A MULTI-THREADING MODE AND FOR GIVING AN ACTIVE THREAD ACCESS TO MULTIPLE REGISTER FILES IN A SINGLE THREAD MODE
| August 7, 2001 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
| January 17, 2002 |
| 6934937 | Multi-channel, multi-service debug on a pipelined CPU architecture
| March 30, 2000 |
| 6931641 | Controller for multiple instruction thread processors
| April 4, 2000 |
| 6931639 | Method for implementing a variable-partitioned queue for simultaneous multithreaded processors
| August 24, 2000 |
| 6928647 | Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
| February 13, 2003 |
| 6915517 | Digital signal processor
| May 15, 2001 |
| 6915414 | Context switching pipelined microprocessor
| July 20, 2001 |
| 6912617 | Altering virtual machine execution parameters at runtime
| July 17, 2002 |
| 6910124 | Apparatus and method for recovering a link stack from mis-speculation
| May 2, 2000 |
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