| 1 2 3 4 5 |
| Patent ID | Title | Date Filed |
| 6981130 | Forwarding the results of operations to dependent instructions more quickly via multiplexers working in parallel
| July 17, 2002 |
| 6981129 | Breaking replay dependency loops in a processor using a rescheduled replay queue
| November 2, 2000 |
| 6981110 | Hardware enforced virtual sequentiality
| October 6, 2002 |
| 6973552 | System and method to handle page validation with out-of-order fetch
| May 12, 2003 |
| 6970996 | Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation
| January 4, 2000 |
| 6952764 | Stopping replay tornadoes
| December 31, 2001 |
| 6944751 | Register renaming to reduce bypass and increase apparent physical register size
| February 11, 2002 |
| 6941447 | High-performance, superscalar-based computer system with out-of-order instruction execution
| November 5, 2003 |
| 6938150 | Processor for managing latest speculation states and efficiently reusing reorder buffer entries
| January 9, 2002 |
| 6934828 | Decoupling floating point linear address
| September 17, 2002 |
| 6928533 | Data processing system and method for implementing an efficient out-of-order issue mechanism
| April 20, 1999 |
| 6925550 | Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
| January 2, 2002 |
| 6920548 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
| April 2, 2004 |
| 6920547 | Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor
| December 20, 2000 |
| 6910121 | System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions
| January 2, 2002 |
| 6901504 | Result forwarding of either input operand to same operand input to reduce forwarding path
| January 22, 2002 |
| 6898695 | Use of a future file for data address calculations in a pipelined processor
| March 28, 2001 |
| 6889317 | Processor architecture
| October 11, 2001 |
| 6889316 | Method and apparatus for restoring registers after cancelling a multi-cycle instruction
| March 28, 2001 |
| 6883086 | Repair of mis-predicted load values
| March 6, 2002 |
| 6880067 | Retiring instructions that meet the early-retirement criteria to improve computer operation throughput
| March 30, 2001 |
| 6877086 | Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
| November 2, 2000 |
| 6870789 | Modified retirement payload array
| February 8, 2002 |
| 6865665 | Processor pipeline cache miss apparatus and method for operation
| December 29, 2000 |
| 6862677 | System and method for eliminating write back to register using dead field indicator
| February 16, 2000 |
| 6859872 | Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation
| May 12, 2000 |
| 6857060 | System, apparatus and method for prioritizing instructions and eliminating useless instructions
| March 30, 2001 |
| 6851044 | System and method for eliminating write backs with buffer for exception processing
| February 16, 2000 |
| 6842851 | Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay
| February 28, 2002 |
| 6839831 | Data processing apparatus with register file bypass
| December 8, 2000 |
| 6826678 | Completion monitoring in a processor having multiple execution units with various latencies
| April 11, 2002 |
| 6826677 | Renaming registers to values produced by instructions according to assigned produce sequence number
| February 6, 2001 |
| 6810474 | Information processor
| August 29, 2000 |
| 6804815 | Sequence control mechanism for enabling out of order context processing
| September 18, 2000 |
| 6792446 | Storing of instructions relating to a stalled thread
| February 1, 2002 |
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