|
| | |
|
Your search returned 245 patents.
( 712/213 in Current US Classification ) |
|
|
| 1 2 3 |
| Patent ID | Title | Date Filed |
| 6415376 | Apparatus and method for issue grouping of instructions in a VLIW processor
| June 16, 2000 |
| 6405303 | Massively parallel decoding and execution of variable-length instructions
| August 31, 1999 |
| 6401144 | Method and apparatus for managing data transfers between peripheral devices by encoding a start code in a line of data to initiate the data transfers
| February 26, 1999 |
| 6397319 | Process for executing highly efficient VLIW
| June 20, 2000 |
| 6393551 | Reducing instruction transactions in a microprocessor
| May 26, 1999 |
| 6385720 | Branch prediction method and processor using origin information, relative position information and history information
| July 13, 1998 |
| 6381689 | Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction
| March 13, 2001 |
| 6378064 | Microcomputer
| March 12, 1999 |
| 6360317 | Predecoding multiple instructions as one combined instruction and detecting branch to one of the instructions
| October 30, 2000 |
| 6360313 | Instruction cache associative crossbar switch
| September 8, 2000 |
| 6351807 | Data processing system utilizing multiple resister loading for fast domain switching
| September 25, 1998 |
| 6351804 | Control bit vector storage for a microprocessor
| October 10, 2000 |
| 6351802 | Method and apparatus for constructing a pre-scheduled instruction cache
| December 3, 1999 |
| 6349381 | Pipelined instruction dispatch unit in a superscalar processor
| July 25, 2000 |
| 6345354 | Register file access
| April 29, 1999 |
| 6339822 | Using padded instructions in a block-oriented cache
| October 2, 1998 |
| 6338132 | System and method for storing immediate data
| December 30, 1998 |
| 1 2 3 |
|
|
|
|
|
|
|
|
|
|
|