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| Patent ID | Title | Date Filed |
| 6625724 | Method and apparatus to support an expanded register set
| March 28, 2000 |
| 6615340 | Extended operand management indicator structure and method
| March 22, 2000 |
| 6604202 | Low power processor
| November 18, 1999 |
| 6567910 | Digital signal processing unit with emulation circuitry and debug interrupt enable register indicating serviceable time-critical interrupts during real-time emulation mode
| February 12, 1999 |
| 6564179 | DSP emulating a microcontroller
| July 26, 1999 |
| 6557094 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
| September 28, 2001 |
| 6532532 | Instruction execution mechanism
| October 15, 1999 |
| 6516295 | Method and apparatus for emulating self-modifying code
| June 30, 1999 |
| 6499098 | Processor with instruction qualifiers to control MMU operation
| October 1, 1999 |
| 6496922 | Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation
| October 31, 1994 |
| 6480952 | Emulation coprocessor
| May 26, 1998 |
| 6463521 | Opcode numbering for meta-data encoding
| June 23, 1999 |
| 6453278 | Flexible implementation of a system management mode (SMM) in a processor
| July 21, 2000 |
| 6449712 | Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
| October 1, 1999 |
| 6446029 | Method and system for providing temporal threshold support during performance monitoring of a pipelined processor
| June 30, 1999 |
| 6442680 | Method and system for compressing reduced instruction set computer (RISC) executable code
| January 29, 1999 |
| 6442675 | Compressed string and multiple generation engine
| July 29, 1999 |
| 6434690 | Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions
| January 11, 1999 |
| 6430674 | Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
| December 30, 1998 |
| 6418527 | Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods
| October 13, 1998 |
| 6415379 | Method and apparatus for maintaining context while executing translated instructions
| October 13, 1999 |
| 6408372 | Data processing control device
| March 2, 2000 |
| 6397319 | Process for executing highly efficient VLIW
| June 20, 2000 |
| 6382846 | Intermediate instruction execution processor which resolves symbolic references without modifying intermediate instruction code
| January 9, 1998 |
| 6367003 | Digital signal processor having enhanced utilization of multiply accumulate (MAC) stage and method
| August 14, 2000 |
| 6363336 | Fine grain translation discrimination
| October 13, 1999 |
| 6356999 | Data processor with trie traversal instruction set extension
| October 16, 2000 |
| 6356995 | Microcode scalable processor
| July 2, 1998 |
| 6351844 | Method for selecting active code traces for translation in a caching dynamic translator
| November 5, 1998 |
| 6349381 | Pipelined instruction dispatch unit in a superscalar processor
| July 25, 2000 |
| 6347392 | Method for the control of an electronic circuit and control unit for its implementation
| December 18, 1998 |
| 6339820 | Method and device for carrying out a function assigned to an instruction code
| April 29, 1999 |
| 6336178 | RISC86 instruction set
| September 11, 1998 |
| 6321322 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
| April 5, 2000 |
| 6317872 | Real time processor optimized for executing JAVA programs
| April 6, 1998 |
| 6317822 | Instruction encoding techniques for microcontroller architecture
| October 3, 1997 |
| 6308256 | Secure execution of program instructions provided by network interactions with processor
| August 18, 1999 |
| 6308255 | Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
| May 26, 1998 |
| 6298434 | Data processing device for processing virtual machine instructions
| October 1, 1998 |
| 6292883 | Converting program-specific virtual machine instructions into variable instruction set
| September 28, 1998 |
| 6292845 | Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively
| August 26, 1998 |
| 6289440 | Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs
| July 14, 1999 |
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