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Your search returned 818 patents.
( 711/144 in Current US Classification )
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Patent IDTitleDate Filed
7133974 Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment August 5, 2002
7133973 Arithmetic processor January 31, 2003
7130965 Apparatus and method for store address for store address prefetch and line locking December 23, 2003
7127562 Ensuring orderly forward progress in granting snoop castout requests June 11, 2003
7127561 Coherency techniques for suspending execution of a thread until a specified memory access occurs December 31, 2001
7124254 Method and structure for monitoring pollution and prefetches due to speculative accesses May 5, 2004
7124236 Microprocessor including bank-pipelined cache with asynchronous data blocks November 26, 2002
7117308 Hypertransport data path protocol April 6, 2004
7114036 Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected January 14, 2004
7111146 Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine June 27, 2003
7107410 Exclusive status tags January 7, 2003
7107405 Writing cached data to system management memory May 30, 2003
7103736 System for repair of ROM programming errors or defects August 11, 2003
7103720 Shader cache using a coherency protocol October 29, 2003
7096323 Computer system with processor cache that stores remote cache presence information September 27, 2002
7093081 Method and apparatus for identifying false cache line sharing January 14, 2004
7089397 Method and system for caching attribute data for matching attributes with physical addresses July 3, 2003
7089376 Reducing snoop response time for snoopers without copies of requested data via snoop filtering May 21, 2003
7089375 Device and method for configuring a cache tag in accordance with burst length June 2, 2005
7089374 Selectively unmarking load-marked cache lines during transactional program execution January 23, 2004
7089372 Local region table for storage of information regarding memory access by other nodes December 1, 2003
7089371 Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory February 11, 2003
7089368 Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory February 11, 2003
7089365 Method and system for an atomically updated, central cache memory July 19, 2005
7089362 Cache memory eviction policy for combining write transactions December 27, 2001
7089357 Locally buffered cache extensions having associated control parameters to determine use for cache allocation on subsequent requests September 22, 2003
7089296 System and method for caching and validating user and command specific server response messages April 25, 2003
7085897 Memory management for a symmetric multiprocessor computer system May 12, 2003
7082501 Remote node accessing local memory by using distributed shared memory April 2, 2003
7082500 Optimized high bandwidth cache coherence mechanism February 18, 2003
7080211 Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory February 11, 2003
7080210 Microprocessor apparatus and method for exclusive prefetch of a cache line from memory February 11, 2003
7080207 Data storage apparatus, system and method including a cache descriptor having a field defining data in a cache block April 30, 2002
7076614 System and method for optimizing bus bandwidth utilization by grouping cache write-backs June 29, 2001
7076613 Cache line pre-load and pre-own based on cache coherence speculation January 21, 2004
7076608 Invalidating cached data using secondary keys December 2, 2003
7076597 Broadcast invalidate scheme October 14, 2003
7073043 Multiprocessor system supporting multiple outstanding TLBI operations per partition April 28, 2003
7073030 Method and apparatus providing non level one information caching using prefetch to increase a hit ratio May 22, 2002
7073026 Microprocessor including cache memory supporting multiple accesses per cycle November 26, 2002
7069384 System and method for cache external writing and write shadowing October 14, 2004
7065613 Method for reducing access to main memory using a stack cache June 6, 2003
7062612 Updating remote locked cache December 12, 2002
7062611 Dirty data protection for cache memories February 7, 2002
7055006 System and method for blocking cache use during debugging April 30, 2003
7051166 Directory-based cache coherency scheme for reducing memory bandwidth loss April 21, 2003
7051159 Method and system for cache data fetch operations June 30, 2003
7047363 Cache memory and control method thereof July 10, 2003
7043610 System and method for maintaining cache coherency without external controller intervention May 5, 2003
7043609 Method and apparatus for protecting a state associated with a memory structure February 3, 2003
7035981 Asynchronous input/output cache having reduced latency December 22, 1998
7035979 Method and apparatus for optimizing cache hit ratio in non L1 caches May 22, 2002
7028151 Information processing device equipped with improved address queue register files for cache miss August 19, 2003
7028150 Arrangement of data within cache lines so that tags are first data received August 23, 2002
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