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Your search returned 203 patents.
( 711/123 in Current US Classification ) |
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| 1 2 3 |
| Patent ID | Title | Date Filed |
| 6457120 | Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions
| November 1, 1999 |
| 6449693 | Method and apparatus for improving caching within a processor system
| April 5, 1999 |
| 6446164 | Test mode accessing of an internal cache memory
| March 14, 1997 |
| 6430683 | Processor and method for just-in-time delivery of load data via time dependency field
| June 25, 1999 |
| 6427207 | Result forwarding cache
| July 20, 2001 |
| 6427190 | Configurable cache allowing cache-type and buffer-type access
| May 12, 2000 |
| 6425074 | Method and apparatus for rapid execution of FCOM and FSTSW
| September 10, 1999 |
| 6393553 | Acknowledgement mechanism for just-in-time delivery of load data
| June 25, 1999 |
| 6393523 | Mechanism for invalidating instruction cache blocks in a pipeline processor
| October 1, 1999 |
| 6389512 | Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same
| December 29, 1999 |
| 6378041 | Shared instruction cache for multiple processors
| March 27, 2001 |
| 6351788 | Data processor and data processing system
| June 10, 1999 |
| 6345354 | Register file access
| April 29, 1999 |
| 6345340 | Cache coherency protocol with ambiguous state for posted operations
| February 17, 1998 |
| 6345335 | Data processing memory system
| September 13, 1999 |
| 6343359 | Result forwarding cache
| May 18, 1999 |
| 6338133 | Measured, allocation of speculative branch instructions to processor execution units
| March 12, 1999 |
| 6334171 | Write-combining device for uncacheable stores
| April 15, 1999 |
| 6330664 | Method relating to handling of conditional jumps in a multi-stage pipeline arrangement
| November 3, 1998 |
| 6330657 | Pairing of micro instructions in the instruction queue
| May 18, 1999 |
| 6321303 | Dynamically modifying queued transactions in a cache memory system
| March 18, 1999 |
| 6308241 | On-chip cache file register for minimizing CPU idle cycles during cache refills
| December 22, 1997 |
| 6292888 | Register transfer unit for electronic processor
| January 27, 1999 |
| 6266744 | Store to load forwarding using a dependency link file
| May 18, 1999 |
| 6253299 | Virtual cache registers with selectable width for accommodating different precision data formats
| January 4, 1999 |
| 6253287 | Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions
| September 9, 1998 |
| 6247097 | Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
| January 22, 1999 |
| 6243791 | Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
| August 13, 1998 |
| 6223260 | Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
| September 10, 1997 |
| 6223254 | Parcel cache
| December 4, 1998 |
| 6212604 | Shared instruction cache for multiple processors
| December 3, 1998 |
| 6199142 | Processor/memory device with integrated CPU, main memory, and full width cache and associated method
| July 1, 1996 |
| 6175896 | Microprocessor system and method for increasing memory Bandwidth for data transfers between a cache and main memory utilizing data compression
| October 6, 1997 |
| 6167486 | Parallel access virtual channel memory system with cacheable channels
| November 18, 1996 |
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