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| Patent ID | Title | Date Filed |
| 6751705 | Cache line converter
| August 25, 2000 |
| 6751704 | Dual-L2 processor subsystem architecture for networking system
| December 7, 2000 |
| 6745262 | Method, system, program, and data structure for queuing requests having different priorities
| January 6, 2000 |
| 6732237 | Multi-tier caching system
| August 29, 2000 |
| 6732124 | Data processing system with mechanism for restoring file systems based on transaction logs
| February 9, 2000 |
| 6728823 | Cache connection with bypassing feature
| February 18, 2000 |
| 6725334 | Method and system for exclusive two-level caching in a chip-multiprocessor
| June 8, 2001 |
| 6718442 | Method and system for using high count invalidate acknowledgements in distributed shared memory systems
| July 20, 2001 |
| 6711652 | Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data
| June 21, 2001 |
| 6708254 | Parallel access virtual channel memory system
| September 27, 2002 |
| 6704844 | Dynamic hardware and software performance optimizations for super-coherent SMP systems
| October 16, 2001 |
| 6694421 | Cache memory bank access prediction
| December 29, 1999 |
| 6687795 | Data processing system and method of communication that reduce latency of write transactions subject to retry
| December 20, 2000 |
| 6681299 | Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method
| March 29, 2000 |
| 6681293 | Method and cache-coherence system allowing purging of mid-level cache entries without purging lower-level cache entries
| August 25, 2000 |
| 6678798 | System and method for reducing memory latency during read requests
| July 20, 2001 |
| 6668306 | Non-vital loads
| June 12, 2001 |
| 6647464 | System and method utilizing speculative cache access for improved performance
| February 18, 2000 |
| 6640289 | Software controlled cache line ownership affinity enhancements in a multiprocessor environment
| January 16, 2001 |
| 6629206 | Set-associative cache-management using parallel reads and serial reads initiated during a wait state
| December 31, 1999 |
| 6629205 | System and method for increasing the snoop bandwidth to cache tags in a cache memory subsystem
| February 23, 2001 |
| 6615332 | Storage system assuring data integrity and asynchronous remote data duplexing
| May 7, 2002 |
| 6611898 | Object-oriented cache management system and method
| April 25, 2001 |
| 6606684 | Multi-tiered memory bank having different data buffer sizes with a programmable bank select
| March 31, 2000 |
| 6604171 | Managing a cache memory
| September 29, 2000 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis
| October 26, 2000 |
| 6594728 | Cache memory with dual-way arrays and multiplexed parallel output
| March 7, 1997 |
| 6591335 | Fault tolerant dual cache system
| September 29, 2000 |
| 6587927 | Data processor having cache memory
| May 25, 2001 |
| 6587922 | Multiprocessor system
| March 30, 2001 |
| 6584546 | Highly efficient design of storage array for use in first and second cache spaces and memory subsystems
| January 16, 2001 |
| 6571324 | Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system
| June 26, 1997 |
| 6571315 | Method and apparatus for cache memory management
| November 20, 2001 |
| 6564309 | DSP architecture optimized for memory accesses
| April 6, 1999 |
| 6557078 | Cache chain structure to implement high bandwidth low latency cache memory subsystem
| February 21, 2000 |
| 6549983 | Cache memory system and method for managing the same
| May 20, 1999 |
| 6546461 | Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein
| November 22, 2000 |
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