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Your search returned 276 patents.
( 710/61 in Current US Classification ) |
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| 1 2 3 |
| Patent ID | Title | Date Filed |
| 6728821 | Method and system for adjusting isochronous bandwidths on a bus
| November 27, 2000 |
| 6728798 | Synchronous flash memory with status burst output
| July 28, 2000 |
| 6725347 | Spin-wheel SDRAM access scheduler for high performance microprocessors
| January 16, 2001 |
| 6721827 | Data processing apparatus and data processing method
| October 25, 2001 |
| 6721813 | Computer system implementing a system and method for tracking the progress of posted write transactions
| January 30, 2001 |
| 6721812 | Method and system for adaptive resource management
| March 22, 2001 |
| 6701390 | FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle
| June 6, 2001 |
| 6691205 | Method for using RAM buffers with simultaneous accesses in flash based storage systems
| March 5, 2001 |
| 6691186 | Dual sequencer based disk formatter
| October 9, 2001 |
| 6678762 | Data processor and data processing method
| March 27, 2001 |
| 6671754 | Techniques for alignment of multiple asynchronous data sources
| August 10, 2000 |
| 6668292 | System and method for initiating a serial data transfer between two clock domains
| March 11, 2002 |
| 6662238 | Integrated modem and line-isolation circuitry with command mode and data mode control and associated method
| January 10, 2000 |
| 6654899 | Tracking bin split technique
| March 28, 2001 |
| 6654824 | High-speed dynamic multi-lane deskewer
| October 3, 2001 |
| 6647444 | Data synchronization interface
| December 29, 2000 |
| 6643720 | Data transfer control method, and peripheral circuit, data processor and data processing system for the method
| August 5, 2002 |
| 6640310 | Clock system for multiple component system
| June 20, 2002 |
| 6640277 | Input staging logic for latching source synchronous data
| May 2, 2002 |
| 6639956 | Data resynchronization circuit
| December 31, 1999 |
| 6631429 | Real-time processing of a synchronous or isochronous data stream in the presence of gaps in the data stream due to queue underflow or overflow
| December 23, 1999 |
| 6625675 | Processor for determining physical lane skew order
| March 23, 2001 |
| 6625665 | Command interpretation system and method
| January 27, 2000 |
| 6625637 | Method and apparatus for synthesizing communication support based on communication types of application
| December 9, 1999 |
| 6609167 | Host and device serial communication protocols and communication packet formats
| March 15, 2000 |
| 6598099 | Data transfer control method, and peripheral circuit, data processor and data processing system for the method
| August 5, 2002 |
| 6597707 | Circuitry, architecture and methods for synchronizing data
| September 8, 1999 |
| 6591354 | Separate byte control on fully synchronous pipelined SRAM
| May 26, 1999 |
| 6584536 | Bus transaction accelerator for multi-clock systems
| October 7, 1999 |
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