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Your search returned 326 patents.
( 710/60 in Current US Classification ) |
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| 1 2 3 4 |
| Patent ID | Title | Date Filed |
| 6839779 | Counting a number of occurrences of a first RTS (ready to send) and a first RTR (ready to receive) signals for limiting a data transfer bandwidth through handshake suppression
| March 18, 2004 |
| 6839778 | Speed power efficient USB method
| June 9, 2000 |
| 6829669 | Bus bridge interface system
| August 17, 2001 |
| 6823407 | Output data path capable of multiple data rates
| February 3, 2003 |
| 6813648 | Method and apparatus for post boot-up domain validation
| July 2, 2001 |
| 6810432 | Method for guaranteeing a device minimun bandwidth on a usb bus
| April 3, 2000 |
| 6804728 | I/O control device and I/O control method
| September 9, 2002 |
| 6795870 | Method and system for network processor scheduler
| April 13, 2000 |
| 6795864 | System using lookup service proxy object having code and request rate for managing rate at which client can request for services from server are transmitted
| December 28, 2000 |
| 6785752 | Method for dynamically adjusting buffer utilization ratios in a hard disk drive system
| March 23, 2001 |
| 6782433 | Data transfer apparatus
| December 26, 2000 |
| 6779058 | Method, system, and program for transferring data between storage devices
| July 13, 2001 |
| 6775724 | Method and apparatus for synchronization control for various frequencies
| February 28, 2001 |
| 6775720 | Method and system for configuring a mass storage system for measuring system performance
| April 4, 2000 |
| 6772245 | Method and apparatus for optimizing data transfer rates between a transmitting agent and a receiving agent
| March 29, 2000 |
| 6772244 | Queuing delay limiter
| May 6, 2002 |
| 6766403 | CPU system with high-speed peripheral LSI circuit
| May 7, 2001 |
| 6766388 | Method for determining a host data transfer goal in a hard disk drive system
| July 27, 2001 |
| 6754740 | Interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface
| December 11, 2000 |
| 6745265 | Method and apparatus for generating status flags in a memory device
| March 21, 2000 |
| 6742061 | Accessory control interface
| September 16, 2002 |
| 6738880 | Buffer for varying data access speed and system applying the same
| June 11, 2001 |
| 6732201 | Hardware speed selection behind a disk array controller
| December 17, 2001 |
| 6732200 | Absorbing jitter during data transmission between applications operating at different frequencies
| November 17, 1999 |
| 6728821 | Method and system for adjusting isochronous bandwidths on a bus
| November 27, 2000 |
| 6728803 | Interconnection architecture for managing multiple low bandwidth connections over a high bandwidth link
| February 11, 2000 |
| 6701387 | Adaptive data fetch prediction algorithm
| August 31, 2000 |
| 6694416 | Double data rate scheme for data output
| September 2, 1999 |
| 6691186 | Dual sequencer based disk formatter
| October 9, 2001 |
| 6687905 | Multiple port input/output job scheduling
| August 11, 2000 |
| 6681275 | Method and apparatus for dynamic coalescing
| September 20, 2001 |
| 6678761 | Method and apparatus for budget development under universal serial bus protocol in a multiple speed transmission environment
| March 30, 2001 |
| 6678756 | Method for controlling a first-in-first-out array to facilitate data transmissions between a lower frequency domain and a higher frequency domain of a computer system
| July 28, 2000 |
| 6678751 | System for setting frame and protocol for transmission in a UART device
| May 12, 2000 |
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