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Your search returned 166 patents.
( 710/116 in Current US Classification ) |
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| Patent ID | Title | Date Filed |
| 6286070 | Shared memory access device and method
| February 25, 1999 |
| 6286068 | Queued arbitration mechanism for data processing system
| August 24, 1998 |
| 6272580 | Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system
| March 16, 1999 |
| 6272579 | Microprocessor architecture capable of supporting multiple heterogeneous processors
| February 22, 1999 |
| 6269360 | Optimization of ordered stores on a pipelined bus via self-initiated retry
| April 24, 1998 |
| 6260100 | System and method for arbitrating interrupts on a daisy-chained architected bus
| January 4, 2000 |
| 6240479 | Method and apparatus for transferring data on a split bus in a data processing system
| July 31, 1998 |
| 6233645 | Dynamically disabling speculative prefetch when high priority demand fetch opportunity use is high
| November 2, 1998 |
| 6216178 | Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution
| November 12, 1999 |
| 6199132 | Communication link with isochronous and asynchronous priority modes
| June 17, 1998 |
| 6199127 | Method and apparatus for throttling high priority memory accesses
| December 24, 1997 |
| 6189059 | Communications system with a master station and at least one slave station
| October 13, 1998 |
| 6185647 | Dynamic bus control apparatus for optimized device connection
| May 14, 1998 |
| 6178475 | Multimedia system employing timers to properly allocate bus access
| December 19, 1994 |
| 6175930 | Demand based sync bus operation
| February 17, 1998 |
| 6157989 | Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system
| June 3, 1998 |
| 6141715 | Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction
| April 3, 1997 |
| 6128676 | DMA control device and recording apparatus having priority control circuit dynamically changes defined priorities within predetermined time interval
| February 6, 1996 |
| 6112270 | Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system
| October 31, 1997 |
| 6105095 | Data packet routing scheduler and method for routing data packets on a common bus
| February 23, 1998 |
| 6092137 | Fair data bus arbitration system which assigns adjustable priority values to competing sources
| November 26, 1997 |
| 6088751 | Highly configurable bus priority arbitration system
| February 12, 1998 |
| 6073199 | History-based bus arbitration with hidden re-arbitration during wait cycles
| October 6, 1997 |
| 6073132 | Priority arbiter with shifting sequential priority scheme
| March 27, 1998 |
| 6029219 | Arbitration circuit for arbitrating requests from multiple processors
| February 25, 1998 |
| 6029217 | Queued arbitration mechanism for data processing system
| October 3, 1994 |
| 6026459 | System and method for dynamic priority conflict resolution in a multi-processor computer system having shared memory resources
| February 3, 1998 |
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