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Your search returned 28 patents.
( 375/215 in Current US Classification ) |
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| 1 |
| Patent ID | Title | Date Filed |
| 7242740 | Digital phase-locked loop with master-slave modes
| April 16, 2003 |
| 7224759 | Methods and apparatus for delay free phase shifting in correcting PLL phase offset
| July 11, 2002 |
| 7139308 | Source synchronous bus repeater
| April 5, 2002 |
| 7133324 | Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same
| December 23, 2004 |
| 7046977 | Apparatus for generating multiple clock signals of different frequency characteristics
| November 4, 2002 |
| 6999480 | Method and apparatus for improving data integrity and desynchronizer recovery time after a loss of signal
| November 26, 2001 |
| 6993095 | Phase-locked loop initialization via curve-fitting
| March 15, 2001 |
| 6807245 | PLO device
| August 5, 2002 |
| 6754234 | Method and apparatus for asynchronous frame synchronization
| May 21, 1999 |
| 6636979 | System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays
| April 13, 2000 |
| 6564160 | Random sampling with phase measurement
| June 22, 2001 |
| 6563893 | Carrier-frequency synchronization system for improved amplitude modulation and television broadcast reception
| May 17, 2001 |
| 6516419 | Network synchronization method and non-break clock switching method in extended bus connection system
| July 29, 1999 |
| 6335952 | Single chip CMOS transmitter/receiver
| July 24, 1998 |
| 6249560 | PLL circuit and noise reduction means for PLL circuit
| December 10, 1996 |
| 5982812 | Method and apparatus for monitoring frequency synthesizer locking time
| May 14, 1997 |
| 5815541 | Digital phase locked loop assembly
| December 9, 1996 |
| 5623512 | Rate converting device capable of determining a transmission rate as desired
| September 14, 1994 |
| 5487084 | Generation of a clock frequency in a smart card interface
| August 11, 1994 |
| 5471502 | Bit clock regeneration circuit for PCM data, implementable on integrated circuit
| May 17, 1994 |
| 5210773 | Process for the intermediate amplification of digital signals and intermediate amplifiers for digital signals
| August 22, 1990 |
| 5090025 | Token ring synchronization
| July 24, 1990 |
| 5052022 | Repeater and PLL circuit
| July 11, 1989 |
| 4881243 | Signal timing circuits
| June 6, 1985 |
| 4691327 | Clock regenerator
| May 6, 1986 |
| 4320515 | Bit synchronizer
| March 7, 1980 |
| 3992581 | Phase locked loop NRZ data repeater
| September 2, 1975 |
| 3962635 | Transmission system for pulse signals of fixed clock frequency using a frequency selective circuit in a clock frequency recovery circuit to avoid phase jitter
| January 17, 1975 |
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