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Your search returned 120 patents.
( 370/518 in Current US Classification ) |
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| 1 2 |
| Patent ID | Title | Date Filed |
| 5818890 | Method for synchronizing signals and structures therefor
| September 24, 1996 |
| 5815504 | PDH/SDH signal processor with dual mode clock generator
| May 13, 1996 |
| 5796792 | Data identifying device and light receiver using the same
| December 29, 1995 |
| 5726988 | Module with data verification for a serial multiplex data system
| November 30, 1995 |
| 5712580 | Linear phase detector for half-speed quadrature clocking architecture
| February 14, 1996 |
| 5706289 | Data module with variable data word length for a serial multiplex data system
| November 30, 1995 |
| 5684841 | Clocking converter for asynchronous data
| October 11, 1994 |
| 5684805 | Microwave multiphase detector
| November 30, 1995 |
| 5671258 | Clock recovery circuit and receiver using same
| December 20, 1994 |
| 5640398 | State machine architecture for concurrent processing of multiplexed data streams
| November 1, 1995 |
| 5608731 | Closed loop clock recovery for synchronous residual time stamp
| March 31, 1995 |
| 5602882 | Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer
| January 19, 1996 |
| 5526361 | Bit demultiplexor for demultiplexing a serial data stream
| July 1, 1993 |
| 5488641 | Digital phase-locked loop circuit
| February 9, 1995 |
| 5473610 | Method of clock signal recovery and of synchronization for the reception of information elements transmitted by an ATM network and device for the implementation of the method
| April 20, 1994 |
| 5442664 | Digitally phase modulated clock inhibiting reduced RF emissions
| December 20, 1993 |
| 5426672 | Process and device for timing recovery
| August 14, 1992 |
| 5402425 | Phase locking circuit for jitter reduction in a digital multiplex system
| September 29, 1993 |
| 5400340 | End of packet detector and resynchronizer for serial data buses
| March 4, 1993 |
| 5394443 | Multiple interval single phase clock
| December 23, 1993 |
| 5386419 | Multiplexer for at least two independently operating signal sources
| August 17, 1993 |
| 5383188 | Receiver having clock phase memory for receiving short preamble time slots
| October 19, 1993 |
| 5361263 | Transmission system for the synchronous digital hierarchy
| November 5, 1993 |
| 5345449 | Clock generation
| February 25, 1993 |
| 5327430 | Circuit arrangement for bit rate adaptation
| December 18, 1992 |
| 5325354 | Synchronous terminal station receiving system
| March 30, 1992 |
| 5309428 | Token ring local area network testing apparatus for phase jitter testing
| January 11, 1993 |
| 5301196 | Half-speed clock recovery and demultiplexer circuit
| March 16, 1992 |
| 5289507 | Clock dejitter circuits for regenerating jittered clock signals
| May 13, 1992 |
| 5228035 | Synchronizing system in digital communication line
| October 29, 1991 |
| 5226046 | Method and apparatus for synchronizing digital data steams
| January 29, 1992 |
| 5210754 | Pattern synchronizing circuit
| June 4, 1991 |
| 5195091 | Adaptive synchronization arrangement
| July 9, 1991 |
| 5181202 | Ring bus station having dual oscillators
| February 6, 1991 |
| 5157651 | Apparatus and method for determining line rates
| July 26, 1990 |
| 5131013 | Asynchronous-synchronous digital transmission signal conversion
| May 30, 1990 |
| 5111455 | Interleaved time-division multiplexor with phase-compensated frequency doublers
| August 24, 1990 |
| 5099477 | Phase matching circuit
| July 19, 1990 |
| 5077761 | Elastic buffer circuit
| May 8, 1990 |
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