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Your search returned 373 patents.
( 365/239 in Current US Classification ) |
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| 1 2 3 4 |
| Patent ID | Title | Date Filed |
| 6600686 | Apparatus for recognizing chip identification and semiconductor device comprising the apparatus
| January 23, 2002 |
| 6597605 | Systems with non-volatile memory bit sequence program control
| May 3, 2002 |
| 6587913 | Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode
| January 31, 2001 |
| 6580659 | Burst read addressing in a non-volatile memory device
| August 25, 2000 |
| 6567313 | Nonvolatile memory, semiconductor device and method of programming to nonvolatile memory
| September 28, 2001 |
| 6560160 | Multi-port memory that sequences port accesses
| November 13, 2000 |
| 6556495 | 2-D FIFO memory having full-width read/write capability
| July 9, 2001 |
| 6542432 | Sub word line drive circuit for semiconductor memory device
| September 26, 2001 |
| 6535442 | Semiconductor memory capable of debugging an incorrect write to or an incorrect erase from the same
| December 17, 2001 |
| 6535420 | Electronically rewritable non-volatile semiconductor memory device
| November 22, 2000 |
| 6529442 | Memory controller with AC power reduction through non-return-to-idle of address and control signals
| January 8, 2002 |
| 6510087 | Semiconductor memory device
| September 25, 2001 |
| 6510069 | Content addressable memory apparatus and method of operating the same
| June 28, 2001 |
| 6504791 | Method for page mode writing in an electrically erasable/programmable non-volatile memory and corresponding architecture
| September 12, 2000 |
| 6501698 | Structure and method for hiding DRAM cycle time behind a burst access
| November 1, 2000 |
| 6493285 | Method and apparatus for sampling double data rate memory read data
| August 9, 2001 |
| 6477101 | Read-ahead electrically erasable and programmable serial memory
| February 28, 2001 |
| 6473357 | Bitline/dataline short scheme to improve fall-through timing in a multi-port memory
| September 29, 2000 |
| 6466512 | Method of generating address configurations for solid state memory
| November 13, 2001 |
| 6466490 | Semiconductor memory circuit
| September 20, 2001 |
| 6456552 | Dynamic register with low clock rate testing capability
| February 1, 2001 |
| 6442645 | Pre-decode conditional command generation for reduced SDRAM cycle latency
| December 4, 1998 |
| 6438054 | Semiconductor integrated circuit
| December 28, 2001 |
| 6425103 | Programmable moving inversion sequencer for memory bist address generation
| September 29, 1999 |
| 6418078 | Synchronous DRAM device having a control data buffer
| December 21, 2000 |
| 6418059 | Method and apparatus for non-volatile memory bit sequence program controller
| June 26, 2000 |
| 6417698 | Linearized digital phase-locked loop method
| December 21, 2000 |
| 6414904 | Two channel memory system having shared control and address bus and memory modules used therefor
| February 6, 2001 |
| 6400644 | Semiconductor control unit
| July 14, 2000 |
| 6388946 | Circuit and method for incrementally selecting word lines
| May 31, 2000 |
| 6385094 | Method and apparatus for achieving efficient memory subsystem write-to-read turnaround through read posting
| September 29, 2000 |
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