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| Patent ID | Title | Date Filed |
| 7197674 | Method and apparatus for conditioning of a digital pulse
| October 10, 2003 |
| 7197438 | System and method for memory compiler characterization
| October 18, 2001 |
| 7196965 | Over driving control signal generator in semiconductor memory device
| July 28, 2005 |
| 7196950 | Non-volatile semiconductor storage device performing ROM read operation upon power-on
| February 16, 2006 |
| 7196949 | Semiconductor memory device with reduced skew on data line
| December 23, 2004 |
| 7196948 | Method and apparatus for data capture on a bi-directional bus
| March 7, 2005 |
| 7196424 | Semiconductor device
| November 8, 2004 |
| 7194053 | System and method for matching data and clock signal delays to improve setup and hold times
| December 18, 2001 |
| 7193921 | Cascade wake-up circuit preventing power noise in memory device
| April 11, 2005 |
| 7193911 | Page buffer for preventing program fail in check board program of non-volatile memory device
| December 9, 2005 |
| 7193910 | Adjustable timing circuit of an integrated circuit
| September 1, 2004 |
| 7193907 | Semiconductor integrated circuit having a power-on reset circuit in a semiconductor memory device
| February 25, 2005 |
| 7190627 | Semiconductor device
| April 28, 2004 |
| 7187608 | System and method for controlling the access and refresh of a memory
| July 28, 2005 |
| 7187599 | Integrated circuit chip having a first delay circuit trimmed via a second delay circuit
| May 25, 2005 |
| 7187598 | Device having an interface and method thereof
| April 5, 2005 |
| 7184920 | Delay measurement system
| May 18, 2004 |
| 7184353 | Semiconductor device
| November 28, 2005 |
| 7184329 | Alignment of memory read data and clocking
| July 8, 2004 |
| 7184328 | DQS for data from a memory array
| October 18, 2004 |
| 7184323 | 4N pre-fetch memory data transfer system
| November 18, 2004 |
| 7180823 | Flexible SDRAM clocking (MS-DLL)
| January 10, 2005 |
| 7180807 | Semiconductor memory device having a delay circuit
| April 20, 2005 |
| 7180800 | Interface circuit for adaptively latching data input/output signal by monitoring data strobe signal and memory system including the interface circuit
| September 16, 2005 |
| 7180791 | Flash with consistent latency for read operations
| December 6, 2004 |
| 7177229 | Apparatus for tuning a RAS active time in a memory device
| September 15, 2004 |
| 7177208 | Circuit and method for operating a delay-lock loop in a power saving manner
| March 11, 2005 |
| 7177207 | Sense amplifier timing
| December 17, 2004 |
| 7177206 | Power supply circuit for delay locked loop and its method
| June 30, 2004 |
| 7177205 | Distributed loop components
| April 27, 2004 |
| 7177204 | Pulse width adjusting circuit for use in semiconductor memory device and method therefor
| June 24, 2004 |
| 7173878 | Apparatus for driving output signals from DLL circuit
| April 21, 2005 |
| 7171321 | Individual data line strobe-offset control in memory systems
| August 20, 2004 |
| 7170819 | Integrated semiconductor memory device for synchronizing a signal with a clock signal
| May 4, 2005 |
| 7170813 | Memory circuit receivers activated by enable circuit
| December 16, 2004 |
| 7170805 | Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods
| February 20, 2004 |
| 7170800 | Low-power delay buffer circuit
| May 9, 2005 |
| 7167401 | Low power chip select (CS) latency option
| February 10, 2005 |
| 7167400 | Apparatus and method for improving dynamic refresh in a memory device
| June 22, 2004 |
| 7161856 | Circuit for generating data strobe signal of semiconductor memory device
| April 27, 2005 |
| 7161855 | Semiconductor memory device and timing control method
| September 17, 2004 |
| 7161854 | Jitter and skew suppressing delay control apparatus
| June 27, 2005 |
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