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| Patent ID | Title | Date Filed |
| 7193885 | Radiation tolerant SRAM bit
| January 5, 2004 |
| 7193437 | Architecture for a connection block in reconfigurable gate arrays
| February 13, 2004 |
| 7190610 | Latch-up prevention for memory cells
| August 31, 2005 |
| 7190609 | Semiconductor memory device with memory cells operated by boosted voltage
| August 26, 2004 |
| 7187614 | Array read access control using MUX select signal gating of the read port
| October 14, 2004 |
| 7184359 | System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock
| December 3, 2004 |
| 7180819 | Converting dual port memory into 2 single port memories
| October 4, 2005 |
| 7180768 | Semiconductor memory device including 4TSRAMs
| June 29, 2004 |
| 7177177 | Back-gate controlled read SRAM cell
| April 7, 2005 |
| 7177176 | Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength
| June 30, 2004 |
| 7173845 | User RAM flash clear
| February 27, 2004 |
| 7173837 | Content addressable memory (CAM) cell bit line architecture
| August 31, 2004 |
| 7170814 | Multi-port semiconductor memory
| February 18, 2004 |
| 7170812 | Semiconductor memory device capable of reducing power consumption during reading and standby
| December 16, 2005 |
| 7170809 | Stable memory with high mobility cell devices
| May 13, 2005 |
| 7170805 | Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods
| February 20, 2004 |
| 7170774 | Global bit line restore timing scheme and circuit
| February 9, 2005 |
| 7167392 | Non-volatile memory cell with improved programming technique
| July 15, 2005 |
| 7167388 | Integrated circuit and method for operating an integrated circuit
| May 26, 2004 |
| 7167024 | Methods and circuitry for implementing first-in first-out structure
| December 31, 2004 |
| 7164616 | Memory array leakage reduction circuit and method
| December 20, 2004 |
| 7164597 | Computer systems
| August 5, 2005 |
| 7164596 | SRAM cell with column select line
| July 28, 2005 |
| 7164593 | Semiconductor integrated circuit
| May 21, 2004 |
| 7161845 | Static random access memory device having a memory cell with multiple bit-elements
| December 23, 2004 |
| 7161828 | Asynchronous static random access memory
| August 9, 2005 |
| 7161827 | SRAM having improved cell stability and method therefor
| January 12, 2005 |
| 7161826 | Low-noise leakage-tolerant register file technique
| June 30, 2004 |
| 7158404 | Power management circuit and memory cell
| July 26, 2004 |
| 7158403 | Ternary bit line signaling
| March 4, 2004 |
| 7158402 | Asymmetric static random access memory device having reduced bit line leakage
| August 6, 2003 |
| 7154770 | Bitcell having a unity beta ratio
| September 25, 2004 |
| 7154764 | Method of controlling a bit line for a content addressable memory
| April 9, 2005 |
| 7149104 | Storage and recovery of data based on change in MIS transistor characteristics
| July 13, 2005 |
| 7143248 | Systems and methods for restoring critical data to computer long-term memory device controllers
| January 27, 2004 |
| 7141835 | Semiconductor memory device having memory cells requiring no refresh operation
| June 16, 2004 |
| 7139190 | Single event upset tolerant memory cell layout
| June 14, 2005 |
| 7139189 | State-retentive mixed register file array
| September 24, 2004 |
| 7136297 | Semiconductor memory device
| March 10, 2005 |
| 7136296 | Static random access memory utilizing gated diode technology
| February 28, 2005 |
| 7133319 | Programmable weak write test mode (PWWTM) bias generation having logic high output default mode
| June 20, 2003 |
| 7126861 | Programmable control of leakage current
| December 30, 2003 |
| 7126858 | Apparatus for emulating asynchronous clear in memory structure and method for implementing the same
| June 17, 2005 |
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