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Your search returned 130 patents.
( 327/163 in Current US Classification ) |
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| Patent ID | Title | Date Filed |
| 6181175 | Clock generator and synchronizing method
| June 29, 1999 |
| 6175258 | Methods and circuits for compensating clock signals having different loads in packaged integrated circuits using phase adjustments
| April 20, 1999 |
| 6157233 | Always-deterministic phase-locked loop
| December 16, 1998 |
| 6154074 | Semiconductor device with test circuit for high accuracy chip testing
| May 5, 1998 |
| 6084452 | Clock duty cycle control technique
| June 30, 1998 |
| 6064707 | Apparatus and method for data synchronizing and tracking
| December 20, 1996 |
| 6044123 | Method and apparatus for fast clock recovery phase-locked loop with training capability
| October 17, 1996 |
| 6041089 | Bit phase synchronizing method and bit phase synchronizing circuit
| January 23, 1997 |
| 6005428 | System and method for multiple chip self-aligning clock distribution
| December 4, 1997 |
| 6002279 | Clock recovery circuit
| October 24, 1997 |
| 5955905 | Signal generator with synchronous mirror delay circuit
| November 10, 1997 |
| 5952853 | Method for extending the output range of pulse-width based phase detectors
| December 23, 1997 |
| 5946363 | Digital detector circuit for recovering the bit timing from a data stream
| December 10, 1996 |
| 5942927 | Clock signal generator for a logic analyzer controlled to lock both edges to a reference clock signal
| December 9, 1997 |
| 5939912 | Recovery circuit having long hold time and phase range
| June 18, 1997 |
| 5920215 | Time-to-charge converter circuit
| June 30, 1997 |
| 5917351 | Relay-race FLL/PLL high-speed timing acquisition device
| August 21, 1997 |
| 5900755 | Phase dither of an acquisition clock using a phase lock loop
| August 11, 1997 |
| 5832047 | Self timed interface
| June 17, 1994 |
| 5818272 | Digital integration gain reduction method
| December 4, 1996 |
| 5805002 | Slow transition time phase frequency detector and method
| August 22, 1996 |
| 5805000 | Logical lose-gain circuit and electronic device having logical loose-gain circuit
| October 18, 1996 |
| 5801562 | Variable delay circuit
| July 25, 1996 |
| 5764712 | Phase locked loop circuit having automatic range setting logic
| April 18, 1996 |
| 5732109 | Phase detector
| December 7, 1995 |
| 5719908 | Digital/analog bit synchronizer
| July 19, 1995 |
| 5710517 | Accurate alignment of clocks in mixed-signal tester
| August 1, 1995 |
| 5654657 | Accurate alignment of clocks in mixed-signal tester
| August 1, 1995 |
| 5638410 | Method and system for aligning the phase of high speed clocks in telecommunications systems
| October 14, 1993 |
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