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| Patent ID | Title | Date Filed |
| 5539337 | Clock noise filter for integrated circuits
| December 30, 1994 |
| 5510732 | Synchronizer circuit and method for reducing the occurrence of metastability conditions in digital systems
| August 3, 1994 |
| 5489865 | Circuit for filtering asynchronous metastability of cross-coupled logic gates
| February 28, 1992 |
| 5487163 | Fast synchronization of asynchronous signals with a synchronous system
| November 4, 1993 |
| 5467037 | Reset generation circuit to reset self resetting CMOS circuits
| November 21, 1994 |
| 5455840 | Method of compensating a phase of a system clock in an information processing system, apparatus employing the same and system clock generator
| September 17, 1993 |
| 5453708 | Clocking scheme for latching of a domino output
| January 4, 1995 |
| 5450024 | ECL to CMOS signal converter circuit including toggle-fault detection
| January 19, 1994 |
| 5446403 | Power on reset signal circuit with clock inhibit and delayed reset
| February 4, 1994 |
| 5365122 | Meta stable resistant signal detector
| December 10, 1992 |
| 5347185 | Protection structure against latch-up in a CMOS circuit
| June 3, 1992 |
| 5233617 | Asynchronous latch circuit and register
| April 13, 1990 |
| 5210449 | Edge triggered tri-state output buffer
| September 16, 1991 |
| 5206545 | Method and apparatus for providing output contention relief for digital buffers
| February 5, 1991 |
| 5168176 | Apparatus and method to prevent the unsettling of a quiescent, low output channel caused by ground bounce induced by neighboring output channels
| July 23, 1991 |
| 5146117 | Convertible multi-function microelectronic logic gate structure and method of fabricating the same
| April 1, 1991 |
| 5138189 | Asynchronous state machine synchronization circuit and method
| September 27, 1990 |
| 5122694 | Method and electrical circuit for eliminating time jitter caused by metastable conditions in asynchronous logic circuits
| December 26, 1990 |
| 5121005 | Programmable logic array with delayed active pull-ups on the column conductors
| April 1, 1991 |
| 5107137 | Master-slave clocked CMOS flip-flop with hysteresis
| September 4, 1990 |
| 5045801 | Metastable tolerant asynchronous interface
| May 29, 1990 |
| 5038327 | Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors
| September 18, 1990 |
| 5036227 | Row address strobe signal input buffer for preventing latch-up
| February 27, 1990 |
| 5036225 | TTL-ECL level converting circuit
| October 6, 1989 |
| 5036221 | Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal
| March 31, 1989 |
| 5029279 | Standard cells with flip-flops located in a single region and having minimal-length clock lines
| July 17, 1989 |
| 5027014 | Translator circuit and method of operation
| March 30, 1990 |
| 5027008 | CMOS clamp circuits
| February 15, 1990 |
| 5014226 | Method and apparatus for predicting the metastable behavior of logic circuits
| September 29, 1988 |
| 5001731 | Method and apparatus for eliminating clockskew race condition errors
| October 2, 1989 |
| 4999528 | Metastable-proof flip-flop
| November 14, 1989 |
| 4983861 | Semiconductor integrated circuit with an input buffer circuit for preventing false operation caused by power noise
| September 25, 1989 |
| 4978869 | ESD resistant latch circuit
| April 19, 1990 |
| 4929850 | Metastable resistant flip-flop
| September 17, 1987 |
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