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| Patent ID | Title | Date Filed |
| 7145361 | Configurable integrated circuit with different connection schemes
| June 30, 2004 |
| 7142010 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization
| December 19, 2003 |
| 7139995 | Integration of a run-time parameterizable core with a static circuit design
| March 19, 2002 |
| 7135888 | Programmable routing structures providing shorter timing delays for input/output signals
| July 22, 2004 |
| 7132850 | Semiconductor integrated circuit and circuit design apparatus
| October 22, 2003 |
| 7129748 | Non-volatile look-up table for an FPGA
| December 29, 2004 |
| 7129747 | CPLD with fast logic sharing between function blocks
| October 15, 2004 |
| 7126381 | VPA interconnect circuit
| June 30, 2004 |
| 7126373 | Configurable logic circuits with commutative properties
| June 30, 2004 |
| 7123051 | Soft core control of dedicated memory interface hardware in a programmable logic device
| June 21, 2004 |
| 7116130 | Method and apparatus for effectively re-downloading data to a field programmable gate array
| December 18, 2003 |
| 7111273 | Softpal implementation and mapping technology for FPGAs with dedicated resources
| July 3, 2003 |
| 7111101 | Method and system for port numbering in an interconnect device
| May 7, 2003 |
| 7109752 | Configurable circuits, IC's, and systems
| June 30, 2004 |
| 7109751 | Methods of implementing phase shift mask compliant static memory cell circuits
| June 2, 2004 |
| 7109750 | Reconfiguration port for dynamic reconfiguration-controller
| April 30, 2004 |
| 7109749 | Programmable logic devices providing reduced power consumption
| May 29, 2003 |
| 7106099 | Decision-feedback equalization clocking apparatus and method
| October 22, 2004 |
| 7106098 | Split FIFO configuration of block RAM
| May 4, 2004 |
| 7102387 | Periodic computation structure based on 1-input lookup tables
| December 8, 2004 |
| 7102386 | Reconfigurable electronic device having interconnected data storage devices
| July 31, 2003 |
| 7102385 | Dedicated input/output first in/first out module for a field programmable gate array
| December 6, 2005 |
| 7102384 | Non-volatile memory architecture for programmable-logic-based system on a chip
| July 22, 2004 |
| 7099227 | PLD hardwire programming with multiple functional modes
| January 16, 2004 |
| 7098690 | Programmable I/O element circuit for high speed logic devices
| December 29, 2004 |
| 7098689 | Disabling unused/inactive resources in programmable logic devices for static power reduction
| September 19, 2003 |
| 7088136 | Programmable logic device latch circuits
| November 6, 2003 |
| 7088132 | Configuring FPGAs and the like using one or more serial memory devices
| October 4, 2005 |
| 7084665 | Distributed random access memory in a programmable logic device
| July 22, 2004 |
| 7081772 | Optimizing logic in non-reprogrammable logic devices
| June 4, 2004 |
| 7080226 | Field programmable gate array (FPGA) configuration data path for module communication
| July 2, 2003 |
| 7075332 | Six-input look-up table and associated memory control circuitry for use in a field programmable gate array
| June 8, 2004 |
| 7071731 | Programmable Logic with Pipelined Memory Operation
| January 21, 2005 |
| 7064579 | Alterable application specific integrated circuit (ASIC)
| June 22, 2004 |
| 7061272 | Finite state machine circuit
| June 30, 2004 |
| 7061271 | Six-input look-up table for use in a field programmable gate array
| June 8, 2004 |
| 7058920 | Methods for designing PLD architectures for flexible placement of IP function blocks
| June 11, 2003 |
| 7049846 | Clock tree network in a field programmable gate array
| August 11, 2004 |
| 7049845 | Programmable delay line using configurable logic block
| March 2, 2004 |
| 7047166 | Method and VLSI circuits allowing to change dynamically the logical behavior
| June 6, 2001 |
| 7046034 | Programmable logic device having heterogeneous programmable logic blocks
| June 3, 2005 |
| 7042263 | Memory clock slowdown synthesis circuit
| December 18, 2003 |
| 7038489 | Method for sharing configuration data for high logic density on chip
| June 14, 2002 |
| 7030650 | Fracturable incomplete look up table area efficient logic elements
| November 10, 2004 |
| 7030646 | Functional pre-configuration of a programmable logic device
| September 2, 2003 |
| 7028107 | Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
| October 7, 2002 |
| 7023240 | Data-driven clock gating for a sequential data-capture device
| July 6, 2004 |
| 7023238 | Input buffer with selectable threshold and hysteresis option
| January 7, 2004 |
| 7015718 | Register file apparatus and method for computing flush masks in a multi-threaded processing system
| April 21, 2003 |
| 7009423 | Programmable I/O interfaces for FPGAs and other PLDs
| May 20, 2005 |
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