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| Patent ID | Title | Date Filed |
| 7183796 | Configuration memory implementation for LUT-based reconfigurable logic architectures
| March 17, 2003 |
| 7180813 | Programmable system device having a shared power supply voltage generator for FLASH and PLD modules
| December 15, 2004 |
| 7177221 | Initializing memory blocks
| December 16, 2004 |
| 7177207 | Sense amplifier timing
| December 17, 2004 |
| 7176714 | Multiple data rate memory interface architecture
| May 27, 2004 |
| 7173451 | Programmable logic circuit apparatus and programmable logic circuit reconfiguration method
| March 17, 2005 |
| 7170316 | Programmable logic array latch
| November 5, 2004 |
| 7170315 | Programmable system on a chip
| May 10, 2004 |
| 7167025 | Non-sequentially configurable IC
| June 30, 2004 |
| 7164290 | Field programmable gate array logic unit and its cluster
| October 26, 2004 |
| 7161383 | Programmable logic device
| October 23, 2003 |
| 7161381 | Multiple size memories in a programmable logic device
| February 25, 2004 |
| 7157938 | Tileable field-programmable gate array architecture
| January 18, 2006 |
| 7157937 | Structured integrated circuit device
| July 22, 2005 |
| 7157936 | Utilization of unused IO block for core logic functions
| January 17, 2003 |
| 7157935 | Method and device for configuration of PLDs
| September 30, 2004 |
| 7157933 | Configurable circuits, IC's, and systems
| June 30, 2004 |
| 7155711 | Method and apparatus providing remote reprogramming of programmable logic devices using embedded JTAG physical layer and protocol
| December 8, 2000 |
| 7154298 | Block-oriented architecture for a programmable interconnect circuit
| December 14, 2001 |
| 7146598 | Method and apparatus for configuring a programmable logic device
| November 19, 2002 |
| 7146441 | SRAM bus architecture and interconnect to an FPGA
| September 18, 2002 |
| 7145361 | Configurable integrated circuit with different connection schemes
| June 30, 2004 |
| 7145360 | Configurable logic element with expander structures
| November 16, 2004 |
| 7143329 | FPGA configuration memory with built-in error correction mechanism
| March 9, 2004 |
| 7142010 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization
| December 19, 2003 |
| 7139995 | Integration of a run-time parameterizable core with a static circuit design
| March 19, 2002 |
| 7135888 | Programmable routing structures providing shorter timing delays for input/output signals
| July 22, 2004 |
| 7135887 | Programmable logic device multispeed I/O circuitry
| December 14, 2004 |
| 7135886 | Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control
| September 20, 2004 |
| 7132852 | Routing architecture with high speed I/O bypass path
| April 14, 2004 |
| 7129748 | Non-volatile look-up table for an FPGA
| December 29, 2004 |
| 7129747 | CPLD with fast logic sharing between function blocks
| October 15, 2004 |
| 7129746 | System-on-a-chip integrated circuit including dual-function analog and digital inputs
| June 25, 2004 |
| 7126856 | Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array
| May 5, 2005 |
| 7126381 | VPA interconnect circuit
| June 30, 2004 |
| 7126374 | Multi-level routing architecture in a field programmable gate array having transmitters and receivers
| March 7, 2005 |
| 7123052 | Interconnection resources for programmable logic integrated circuit devices
| March 22, 2005 |
| 7117373 | Bitstream for configuring a PLD with encrypted design data
| November 28, 2000 |
| 7116573 | Switching element method of driving switching element rewritable logic integrated circuit and memory
| July 16, 2004 |
| 7116130 | Method and apparatus for effectively re-downloading data to a field programmable gate array
| December 18, 2003 |
| 7114069 | Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor
| April 22, 2003 |
| 7112992 | Configuration shift register
| December 8, 2004 |
| 7111273 | Softpal implementation and mapping technology for FPGAs with dedicated resources
| July 3, 2003 |
| 7111224 | FPGA configuration memory with built-in error correction mechanism
| February 28, 2001 |
| 7111214 | Circuits and methods for testing programmable logic devices using lookup tables and carry chains
| October 9, 2002 |
| 7109751 | Methods of implementing phase shift mask compliant static memory cell circuits
| June 2, 2004 |
| 7109750 | Reconfiguration port for dynamic reconfiguration-controller
| April 30, 2004 |
| 7109748 | Integrated circuits with reduced standby power consumption
| June 7, 2005 |
| 7109743 | Integrated circuit output driver circuitry with programmable preemphasis
| June 7, 2005 |
| 7106099 | Decision-feedback equalization clocking apparatus and method
| October 22, 2004 |
| 7102387 | Periodic computation structure based on 1-input lookup tables
| December 8, 2004 |
| 7102386 | Reconfigurable electronic device having interconnected data storage devices
| July 31, 2003 |
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