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| Patent ID | Title | Date Filed |
| 6500706 | Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM
| March 19, 2001 |
| 6479377 | Method for making semiconductor devices having contact plugs and local interconnects
| June 5, 2001 |
| 6479366 | Method of manufacturing a semiconductor device with air gaps formed between metal leads
| February 20, 2001 |
| 6465331 | DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines
| August 31, 2000 |
| 6458692 | Method of forming contact plug of semiconductor device
| February 22, 2002 |
| 6456518 | Bi-level digit line architecture for high density drams
| August 28, 2001 |
| 6455886 | Structure and process for compact cell area in a stacked capacitor cell array
| August 10, 2000 |
| 6451651 | Method of manufacturing DRAM device invention
| August 20, 2001 |
| 6433994 | Capacitor constructions
| May 11, 2001 |
| 6433381 | Semiconductor device and method of manufacturing the same
| January 9, 2001 |
| 6429529 | Bi-level digit line architecture for high density drams
| March 23, 2000 |
| 6429476 | Semiconductor integrated circuit device
| March 1, 2001 |
| 6429474 | Storage-capacitor electrode and interconnect
| April 11, 2000 |
| 6429473 | DRAM cell with stacked capacitor self-aligned to bitline
| July 30, 1996 |
| 6423641 | Method of making self-aligned bit-lines
| September 18, 2000 |
| 6407420 | Integrated circuit device having line width determined by side wall spacer provided in openings formed in insulating film for connection conductors
| June 17, 1999 |
| 6396727 | Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same
| February 15, 2000 |
| 6388282 | Semiconductor memory device and method of manufacture the same
| November 24, 2000 |
| 6376380 | Method of forming memory circuitry and method of forming memory circuitry comprising a buried bit line array of memory cells
| August 30, 2000 |
| 6373090 | Scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise
| September 5, 2000 |
| 6372575 | Method for fabricating capacitor of dram using self-aligned contact etching technology
| June 28, 2000 |
| 6359301 | Semiconductor device and method of manufacturing the same
| June 24, 1998 |
| 6350650 | Method for fabricating a semiconductor memory device
| November 14, 2000 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
| June 19, 2000 |
| 6344389 | Self-aligned damascene interconnect
| April 19, 1999 |
| 6335237 | Methods of forming capacitor and bitline structures
| March 3, 2000 |
| 6329255 | Method of making self-aligned bit-lines
| July 20, 2000 |
| 6329241 | Methods for producing capacitor-node contact plugs of dynamic random-access memory
| May 2, 2000 |
| 6326659 | Semiconductor memory and method of manufacturing same
| December 30, 1999 |
| 6312985 | Method of fabricating a bottom electrode
| October 10, 2000 |
| 6312983 | Etching method for reducing bit line coupling in a DRAM
| October 21, 1999 |
| 6310399 | Semiconductor memory configuration with a bit-line twist
| February 28, 2000 |
| 6303429 | Structure of a capacitor section of a dynamic random-access memory
| October 2, 2000 |
| 6303424 | Method for fabricating a buried bit line in a DRAM cell
| October 21, 1999 |
| 6300667 | Semiconductor structure with air gaps formed between metal leads
| August 25, 1998 |
| 6291335 | Locally folded split level bitline wiring
| October 4, 1999 |
| 6287914 | Method of forming a MISFET device with a bit line completely surrounded by dielectric
| August 17, 2000 |
| 6268280 | Semiconductor device using dual damascene technology and method for manufacturing the same
| November 9, 1998 |
| 6268243 | Method for fabricating dynamic random access memory cells
| October 6, 1999 |
| 6258661 | Formation of out-diffused bitline by laser anneal
| August 30, 2000 |
| 6255686 | Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof
| July 30, 1998 |
| 6255685 | Semiconductor device and method of manufacturing the same
| November 12, 1997 |
| 6255224 | Method of forming contact for semiconductor device
| August 16, 1999 |
| 6255168 | Method for manufacturing bit line and bit line contact
| September 13, 1999 |
| 6249452 | Semiconductor device having offset twisted bit lines
| September 22, 1999 |
| 6245631 | Method of forming buried bit line memory circuitry and semiconductor processing method of forming a conductive line
| December 6, 1999 |
| 6242809 | Integrated circuit memory devices including titanium nitride bit lines
| March 23, 1999 |
| 6239014 | Tungsten bit line structure featuring a sandwich capping layer
| August 16, 1999 |
| 6235572 | Method of making a memory cell having two layered tantalum oxide films
| June 17, 1999 |
| 6218236 | Method of forming a buried bitline in a vertical DRAM device
| January 28, 1999 |
| 6218232 | Method for fabricating DRAM device
| December 29, 1998 |
| 6207493 | Formation of out-diffused bitline by laser anneal
| August 19, 1998 |
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