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Your search returned 342 patents.
( 257/202 in Current US Classification ) |
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| 1 2 3 4 |
| Patent ID | Title | Date Filed |
| 6900478 | Multi-threshold MIS integrated circuit device and circuit design method thereof
| October 11, 2002 |
| 6897571 | Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
| October 1, 2002 |
| 6897499 | Semiconductor integrated circuit device including MISFETs each with a gate electrode extended over a boundary region between an active region and an element isolation trench
| February 7, 2003 |
| 6894532 | Programmable logic arrays with ultra thin body transistors
| December 17, 2002 |
| 6885046 | Semiconductor integrated circuit configured to supply sufficient internal current
| January 29, 2002 |
| 6885044 | Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates
| July 30, 2003 |
| 6885043 | ASIC routing architecture
| January 18, 2002 |
| 6881989 | Semiconductor integrated circuit having high-density base cell array
| June 12, 2003 |
| 6880145 | Method for determining die placement based on global routing architecture
| December 21, 2001 |
| 6876014 | Interconnection structure of a semiconductor device
| June 28, 2002 |
| 6872990 | Layout method of semiconductor device
| December 9, 1999 |
| 6870205 | Scalable hierarchical I/O line structure for a semiconductor memory device
| January 7, 2003 |
| 6864518 | Bit cells having offset contacts in a memory array
| May 14, 2003 |
| 6850289 | Array substrate for liquid crystal display device
| June 9, 2003 |
| 6841832 | Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance
| December 19, 2001 |
| 6838711 | Power MOS arrays with non-uniform polygate length
| September 8, 2003 |
| 6836026 | Integrated circuit design for both input output limited and core limited integrated circuits
| July 3, 2003 |
| 6835970 | Semiconductor device having self-aligned contact pads and method for manufacturing the same
| March 1, 2002 |
| 6831317 | System with meshed power and signal buses on cell array
| December 10, 2002 |
| 6828604 | Semiconductor device with antenna pattern for reducing plasma damage
| May 2, 2002 |
| 6816399 | Semiconductor memory device including ferroelectric memory formed using ferroelectric capacitor
| March 28, 2003 |
| 6815709 | Structure having flush circuitry features and method of making
| May 23, 2001 |
| 6812506 | Polysilicon linewidth measurement structure with embedded transistor
| November 19, 2002 |
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device
| August 18, 1999 |
| 6806515 | Layout of a decoder and the method thereof
| January 15, 2002 |
| 6806514 | Modular digital pixel sensor system
| October 24, 2001 |
| 6802043 | Semiconductor device having a function block provided in a macro and operating independently of the macro and method for designing the same
| March 28, 2002 |
| 6800884 | Inter-tile buffer system for a field programmable gate array
| December 30, 2002 |
| 6791353 | Enhanced field programmable gate array
| September 25, 2000 |
| 6784558 | Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads
| July 11, 2003 |
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